IIT (ISM) Dhanbad JRF Recruitment 2026 invites applications for one Junior Research Fellow post in Electronics Engineering under a TTDF-funded 6G Silicon Photonics research project. Candidates with M.Tech., M.E., M.S., B.Tech., or M.Sc. along with GATE/NET qualification can apply online before 17 August 2026.

Date Posted: : 1st August 2026

Organization: Indian Institute of Technology (Indian School of Mines), Dhanbad (IIT (ISM) Dhanbad)

Organization Profile

Indian Institute of Technology (Indian School of Mines), Dhanbad, an Institute of National Importance, is one of India’s premier institutions for engineering, science, technology, and research. Established in 1926 and granted IIT status in 2016, the institute is renowned for its cutting-edge research, innovation, and academic excellence across various engineering and scientific disciplines.

The Department of Electronics Engineering invites applications for the post of Junior Research Fellow (JRF) under a research project funded by the Telecommunication Technology Development Fund (TTDF) Scheme of the Department of Telecommunications (DoT), Government of India, through TCOE India.

Recruitment Details

Organization: Indian Institute of Technology (Indian School of Mines), Dhanbad

Department: Electronics Engineering

Position: Junior Research Fellow (JRF)

Number of Vacancies: 01

Project Number: SRDP 1176G

Employment Type: Temporary (Project-Based)

Notification Date: 28 July 2026

Project Details

Project Title

“Silicon Photonic Chip-Based N × N Photonic Switches for 6G and Beyond”

Funding Agency

Department of Telecommunications (DoT), Government of India

Scheme: Telecommunication Technology Development Fund (TTDF)

Implementing Agency: TCOE India

Project Duration

• Initial appointment for one year.
• Extendable based on satisfactory performance and project requirements.
• Maximum tenure: Two years or till the completion of the project, whichever is earlier.

Educational Qualification

Candidates must possess First Class with minimum 60% marks (or equivalent CGPA) in any one of the following:

• M.Tech./M.E./M.S. in Electronics
• Electronics & Communication Engineering
• Electronics & Telecommunication Engineering
• Related Engineering disciplines
• B.Tech./B.E. in Electronics & Communication Engineering
• Electronics & Telecommunication Engineering
• M.Sc. in Electronics
• M.Sc. in Physics with specialization in Electronics or Photonics

Additionally, candidates must have qualified:

• GATE, or
• NET

Desirable Skills

Preference will be given to candidates having knowledge of:

• Photonic Integrated Circuits (PIC)
• Silicon Photonics
• Optical Communication Systems
• Microelectronics
• Optoelectronics
• Nanotechnology
• VLSI Design
• ANSYS Lumerical
• MATLAB
• Semiconductor Device Simulation

Job Responsibilities

The selected Junior Research Fellow will be responsible for:

• Designing integrated silicon photonic N × N optical switches.
• Performing FDTD and INTERCONNECT simulations.
• Preparing fabrication-ready layouts using PDK and KLayout.
• Conducting device-level and system-level characterization.
• Assisting in research publications and technical documentation.
• Supporting project implementation and collaboration activities.

Fellowship

First & Second Year

₹37,000 per month

Third Year (As mentioned in the project notification)

₹42,000 per month

Age Limit

• Maximum 35 years.
• Age relaxation is applicable for SC/ST/OBC/PwD/Women candidates as per Government of India norms.

How to Apply

Eligible candidates should complete the online application form and upload the following documents:

• Self-attested educational certificates and mark sheets.
• GATE/NET qualification certificate.
• Updated Curriculum Vitae (CV) with recent photograph.
• Experience certificate (if applicable).
• Age proof.
• Category certificate (if applicable).
• List of publications, awards, and achievements (if any).
• Recommendation letter.

Last Date to Apply: 17 August 2026 (up to 4:00 PM)

Candidates are advised to carefully read the official notification before submitting the application.

Project Investigator

Prof. Devendra Chack
Associate Professor
Department of Electronics Engineering
Indian Institute of Technology (ISM), Dhanbad

Email: devendra@iitism.ac.in

Selection Process

The selection process may include:

• Scrutiny of applications.
• Shortlisting based on qualifications and experience.
• Personal interview (online/offline as notified).
• Document verification.
• Final selection based on merit and project requirements.

Note: Only shortlisted candidates will be invited for the interview. No TA/DA will be paid for attending the selection process.

Address

Department of Electronics Engineering
Indian Institute of Technology (Indian School of Mines), Dhanbad
Dhanbad – 826004,
Jharkhand, India.

Official Website: https://www.iitism.ac.in